OVERVIEW

The C2C (Chip-to-Chip) interface IP is a high-performance, low-latency, and power-efficient chip-to-chip interconnect solution designed for advanced multi-chiplet systems, AI accelerators, high-speed computing, and networking SoCs. It enables seamless, reliable data transmission between separate chips or heterogeneous dies through package interposer or PCB traces.

MSquare offers this silicon-proven IP with unique hybrid analog/digital architecture which has low power, compact area and robust performance. This UCIe&C2C combo IP contains Die-to-Die adapter layer and physical layer, each layer contains a sideband interface to provide a back-channel for link training and access of registers of the link partner.

HIGHLIGHTS

C2C&D2D Combo (UCIe-based) IP compliant with UCIe specification

Standard Package with PCB, channel reach up to 100mm

16-TX and 16-RX per-module, IO rate up to 32Gbps and independent full-duplex

Total solution with Controller+PHY

Supports AXI4/CXS.b interface (512-bit data width @1GHz Clock)