OVERVIEW

The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package. MSquare's D2D solution, compatible with the UCIe v1.1 specification, includes both a Die-to-Die adapter layer and a physical layer. Each layer features a sideband interface that provides a back-channel for link training and access to the registers of the link partner, as shown in Figure 1. This unique hybrid analog/digital architecture offers low power consumption, compact footprint, and robust performance, making it well-suited for target applications such as high-performance computing, AI, or multimedia SoCs, and Die-to-Die interconnections.

HIGHLIGHTS

Compatible with UCIe v1.1 specification

Features single-ended, source-synchronous, and DDR I/O signaling

Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages

Offers a high clock frequency up to 16GHz

Provides data transfer rate up to 32Gbps per lane

Delivers 1Tbps (512Gbps TX + 512Gbps RX) bandwidth per module for standard packages

High energy efficiency with ~0.8pJ/bit for standard packages

Built-in test and diagnostics [Functional (PRBS), scan, at-speed external loopback]

The advanced 12nm/6nm process