OVERVIEW

The LPDDR6 PHY IP is a high-speed, low-power physical layer interface IP designed for next-generation mobile memory, automotive applications, and high-bandwidth SoCs requiring power-efficient memory connectivity. It complies with the latest LPDDR6 standard and supports high-speed data transfer rates with advanced signal integrity and power management features.

MSquare' LPDDR6 IP is a transceiver IP between DRAM controller and DRAM device. Supporting DFI5.1 as a universal IP protocol. The maximum data rate of LPDDR6, LPDDR5X, LPDDR5 and LPDDR4X can reach 14400Mbps, 8533Mbps, 6400Mbps and 4266Mbps respectively with 16bit data width per channel. Figure 1 is LPDDR6 PHY block diagram in system application, which includes Data, Address transmit path, Receiver data path and PLL block, etc.

HIGHLIGHTS

Compatible with JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs

Support 10.667Gbps~14.400Gbps with BL=24/BL=48 and will be expanded to 16Gbps in the future

Support Dual sub channel architecture (2x12 bit), 32B minimal access granularity

Support Dynamic Efficiency Mode (DEM) + Static Efficiency Mode (SEM) for runtime power performance trade off

Support Dynamic NT-ODT

Support PHY Independence TX/RX Training mode

Support self-test mode with built-in bist

Support ZQ calibration, DFE mode

PLL & DLL included